Design and implementation of a 64bit cmos parallel adder with modified architecture 并行加法器設(shè)計(jì)與實(shí)現(xiàn)
Computers , 2005 , 54 : 225 - 231 . 2 brent r p , kung h t . a regular layout for parallel adders 并行前綴加法器可分為g p產(chǎn)生部分進(jìn)位傳播部分或稱為進(jìn)位鏈以及結(jié)果產(chǎn)生部分。
parallel adderとは意味:並列加算器{へいれつ かさん き} parallel adder meaning:[Electronics] In a computer or calculator, an adder in which corresponding digits in multibit numbers are added simultaneously. Also see PARALLEL, 1. parallel antenna tuning Antenna-feeder tuning in ...parallel adder перевод:сумматор параллельного действия, параллельный сумматор